Class a-b pulse width modulating amplifiers



Dec. 29, 1970 J. c. ENGEL.

CLASS A-B PULSE WIDTH MODULATING AMPLIFIERS Filed May 2'?, 1968 5. M rM 1. WA liv l Il .vl l .f/Ml 7 A I// O O O B H *v1 J I.- 3 C D E4 L 6 HA T 2 A @M Fw E Tmn.. In" A E W Mm N W M\l SG .m G O E P N m` TLE AC U RPmi: mmo S S T'ME* INVENTOR Joseph C. Engel WITNESSES:

j @Mmx' BY/ MV" United States Patent Oice 3,551,85l Patented Dec. 29,1970 U.S. Cl. 332-9 5 Claims ABSTRACT OF THE DISCLOSURE A pulse widthmodulated amplifier is disclosed capable of being operated in the classA-B amplifying mode and employing double-edge modulation. In theamplifier, a source of modulating signals is provided which may have,for example, a sawtooth waveform. The sawtooth waveform is respectivelyclamped to opposite polarities in the two channels of the amplifier. Inone channel of the amplifier the input signal thereto and a biasingpotential are compared with one polarity of the clamped sawtooth, withthe comparison thereof determining the pulse duration of output signalsof one polarity. In the other channel of the amplifier, the inputsignals and a biasing potential are compared with the clamped sawtoothof the other polarity, with the duration of the output pulses beingdependent upon this comparison. The output pulses are supplied byswitching devices, such as transistors, whose duty cycle is controlledby the comparison in the respective channels of the amplifier.

BACKGROUND OF THE INVENTION The present invention relates to pulse widthmodulated amplifiers and, more particularly, to pulse width modulatedamplifiers which may be operative in a class A-B amplify mode.

In copending application Ser. No. 696,894 filed Ian. 10, 1968, nowabandoned, by same inventor as the present application, a pulse widthmodulated (PWM) amplifier is disclosed capable of operation in a classA-B amplifying mode. A single-edge modulating technique is utilized inthe amplifier of the copending application wherein a pair of modulatingwaveforms, each having a ramp waveshape (i.e. linearly increasing intime With a short retrace time) are generated 180 out of phase with eachother. The ramp modulating waveforms are respectively used in thepositive and negative channels of the amplifier wherein each waveform iscompared with the input signals to the amplifier and respective biasingpotentials. In response to this comparison, control signals ofcorresponding pulse durations are generated which are utilized tocontrol the duty cycle of a pair of controlled switching devices, suchas silicon controlled rectfiers or transistors. In this fashion, a pulsewidth modulated output is supplied to a load coupled to the switchingdevices. Respective bias potentials supplied in each of the channelsprovide a small duty cycle of operation for the switching devices underno input signal conditions and thereby provide a class A-B mode ofoperation for the amplifier. The ramp modulating waveforms must besubstantially 180 out of phase with each other to prevent both of thecontrolled switching devices from being turned on at the same time andthereby creating a short circuit across the amplifier. It is thereforenecessary that the modulating signal generator by synchronized toprovide the two ramp waveforms at approximately apart. Moreover, themodulating ramp waveforms must have fast retrace times.

SUMMARY OF THE INVENTION The present invention broadly provides a pulsewidth modulated amplifier wherein modulating signals are respectivelyclamped to permit excursions in opposite polarities to be used asreference signals in a first and second channel of the amplifier. Theclamped reference signals are compared with input and biasing signals inthe respective channels to provide control signals whose duration isdependent upon the comparison. The biasing signals are utilized topermit class A-B operation of the amplifier, and the control signals areutilized 4for controlling the output of the amplifier to provide outputsignals having a time duration corresponding to the control signals.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block-schematic diagram ofthe pulse width modulated amplifier of the persent invention;

FIGS. 2 and 3 are waveform diagrams each including a set of curves usedin explaining the operation of the amplifier of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1 the PWM amplifier isshown having a positive channel and a negative channel with the channelsbeing supplied by an input signal source S. The input signal source Smay supply, for example, audio frequency signals having a sinusoidalwaveshape between its output lead S1 and ground. It should beunderstood, however, that the output of the input signal source S mayhave various waveforms and frequencies.

The input signals from the lead S1 of the input signal source S aresupplied, respectively, via a resistor R1 and a resistor R2 to the baseelectrode of a transistor Q1 in the positive channel and to the baseelectrode of a transistor Q2 in the negative channel.

A sawtooth generator M is provided which supplies an output waveform Das shown in curve D of FIG. 2. The waveform D is a sawtooth waveformvarying about a zero ground reference potential and has a triangularshape as shown in curve D of FIG. 2. In the positive channel a negativeclamping circuit including a capacitor C1 and a diode D1 is provided,and in the negative channel a positive clamping circuit including acapacitor C2 and a diode D2 is provided. The capacitor C1 is connectedbetween the point D at the output of the sawtooth generator M and apoint C to which the anode of the diode D1 is connected. The cathode ofthe diode D1 is grounded. The capaictor C2 is connected between thepoint D and a point E to which the cathode of the diode D2 is connected,with the anode of the diode D2 being returned to ground. Thus thenegative clamping circuit C1-D1 clamps the sawtooth waveform Dnegatively to ground permitting only negative polarity excursions. Thewaveform at the point C at the anode of the diode D1 is shown in curve Cof FIG. 2. Conversely the positive clamping 3 circuit C2-D2 permits onlypositive excursions of the sawtooth waveform D of this waveform and isshown in curve E of FIG. 2 appearing at the point E at the cathode ofdiode D2.

The output of the negative clamp circuit C1-D1, as shown in curve C ofFIG. 2, is supplied via a resistor R3 to the base of the transistor Q1at a point B. A diode D3 is connected from anode to cathode between theemitter and base electrodes of the NPN transistor Q1 to protect thisjunction against excessive reverse voltage and currents. The output ofthe positive clamping circuit C2-D2, as shown in curve E of FIG. 2, issupplied via a resistor R4 to the base electrode of the transistor Q2 ata point F. A diode D4 is connected from anode to cathode between thebase and emitter electrodes of the PNP transistor Q2 to protect thisjunction.

A positive biasing potential B-{- is supplied via a resistor R5 to thepoint B at the base of the transistor Q1 which is of the NPN type. Thenegatively clamped waveform of curve C is algebraically added to thepositive biasing voltage B+ at the point B to supply a waveform as shownin curve B of FIG. 2 for a no input case, i.e. with no input signalsbeing supplied by the source S. It can be seen from curve B of FIG. 2that this waveform has a small positive portion thereof having a peakamplitude B-ldue to the biasing potential B-iduring each cycle of themodulating waveform shown in curve D.

A negative biasing potential B- is supplied via a resistor R6 to thepoint F at the base of the transistor Q2, which is of the PNP type to besummed with the waveform shown in curve E of FIG. 2. The resultingwaveform is shown as at curve F in FIG. 2 and has a negative portionhaving a peak negative magnitude B- due to the negative bias potentialB- during each cycle of the modulating waveform of curve D for the noinput signal case. The amount of time that the waveform B is positiveand the waveform F is negative can be adjusted by selecting the valuesof the positive basing potential B-I- and negative biasing potential B-,respectively.

A positive operating potential V-lis applied to the collector of thetransistor Q1 via a resistor fR`7. A series circuit including acapacitor C3 and a primary winding W1 of a transformer T1 is connectedbetween the collector and emitter electrodes of the transistor Q1, withthe dotted end of the winding W1 being connected to the emitterelectrode. During the time period that the transistor Q1 isnon-conductive the capacitor C1 will be charged to substantially theV-lpotential via the resistor R7. When the waveform B goes positive thebase-emitter circuit of the transistor Q1 will be forward biased and thetransistor will be rendered conductive with the capacitor C1 dischargingthrough the collector-emitter circuit of transistor Q1 into the dottedend of the winding W1. The transformer T1 includes a secondary windingW2 which has its dotted end connected via a resistor R8 to the baseelectrode of an output transistor Q3. The undotted end of the winding W2is connected to the emitter electrode of the transistor Q3 thereof. Thuswith the capacitor C3 discharging into the dotted end of the winding W1,base current is supplied from the dotted end of the winding W2 via theresistor R8 into the base of the transistor Q3 turning on thistransistor which is of the NPN type. The collector of the transistor Q3is connected to a source of positive potential .A-iand the emitterelectrode thereof is connected via a load impedance Z to ground. Theoutput at the emitter of the transistor Q3 is shown in curve A of FIG. 2`with the duration of this output pulse being equal to the time periodthat the Waveform of curve B is positive to maintain the transistor Q1in a conduction y state. When the transistor Q1 is renderednon-conductive at the time the negatively clamped modulating waveform Cgoes suiciently negative, base drive will be removed from the transistorQ3 thereby turning it o` and terminating the output pulse as applied tothe load impedance Z.

The operation in the negative channel is analogous to that of thepositive channel. With the transistor Q2 nonconductive, a capacitor C4,connected to the collector thereof, will charge from a negativeoperating potential B- via a resistor R9 which is coupled to thecollector of the transistor Q2. A primary winding W3 of a transformer T2is connected between the other end of the capacitor C4 and the emitterof the transistor Q2, with the undotted end of the winding W3 connectedto the emitter of the transistor Q2. The transistor Q2 is renderedconductive when the waveform of curve F of FIG. 2 goes negative toforward bias the base-emitter junction of the PNP transistor, Q2. Theturning on of the transistor Q2 causes the capacitor C4 to dischargeinto the dotted end of the winding W3 and through the emitter-collectorcircuit of the transistor Q2. Due to the dot convention on thetransformer T2, current ow is induced out of the dotted end of asecondary winding W4 of the transistor T2 and applied via a resistor R10to the base of an output transistor Q4 of the NPN type thereby turningthis transistor on. The colector of the transistor Q4 is connected tothe load impedance Z and the emitter of the transistor Q3, and theemitter electrode of the transistor Q4 is connected to a source ofnegative potential A-. The turning on of the transistor Q4 essentiallyclamps the collector thereof at the point G to the A- potential therebyproviding a pulse output as shown in curve G of FIG. 2. A current pathis thus provided through the load impedance Z in the opposite directionfrom that provided during the positive half of the operating cycle. Thiscurrent path is from ground through the load irnpedance Z and thecollector-emitter circuit of transistor Q4 to the A source.

The transistor Q2 remains conductive as long as the waveform as shown incurve F of FIG. 2 remains negative as determined by the B- potential.When the waveform goes positive under the influence of the positivemodulating signal shown in curve 'E of FIG. 2, transistor Q2 will beturned off thereby terminating base-drive current to the transistor Q4which will thereby be rendered non-conductive. The time duration of thenegative output pulse as thus shown in curve G of FIG. 2 is thusdetermined by the time period that the waveform F of FIG. 2 remainsnegative. The composite output waveform as seen by the load impedance Zis shown in curve H of FIG. 2 for the no input signal case and is shownto be comprised of positive and negative going pulses whose timedurations are dependent, respectively, on the positive and negativemagnitudes of the positive biasing potential B-land the negative biasingpotential B- for the no input signal case.

A diode DS is connected from anode to cathode between the emitter andbase electrodes of the output transistor Q3, and a diode D6 is connectedfrom anode to cathode between the emitter and base electrodes of thetransistor Q4. The function of the diodes DS and D6 is to protect therespective base-emitter junctions of these transistors from excessivereverse voltages and currents which would be destructive of the outputdevices.

The load impedance Z is shown schematically as a resistive load;however, it may include reactive components which may cause reactiveload currents to appear as the respective power transistors are turnedoff. In order t0 accommodate any reactive currents, a diode D7 isconnected from anode to cathode between the emitter and collectorelectrodes of the transistor Q3, and a diode D8 is connected from anodeto cathode between the emitter and collector electrodes of thetransistor Q4. The diodes D7 and D8 may comprise fast recovery diodesand are operative to circulate any reactive load current which might bepresent in the output load circuit back to the power supply supplyingthe voltages A+ and A-. Thus, as the transistor Q3 is being turned off,the diode D8 would circulate any inductive load current therethroughback to the A supply, and, when the output transistor Q4 is being turnedoff, the diode D7 would circulate any inductive load currenttherethrough back to the A+ supply voltage. The use of the diodes D7 andD8 prevents any destructive voltage transients from being applied acrossthe respective output transistors Q3 and Q4 at the time of being turnedoff. The load impedance Z may, for example, comprise a loudspeaker, and,in that case, it may be necessary to neutralize the coil thereof by theuse of a series resistor and capacitor across the coil to insure thereactive current ow is minimized.

Referring to FIG. 3 the operation of the PWM amplifier in FIG. 1 will bediscussed for the case when an input signal is applied thereto such asshown in curve S1 of FIG. 3 wherein the input signal has a positivepotential of V1-|- for a period of time which then reversed to anegative polarity voltage V1-. It should be noted that the sawtoothmodulating waveform appearing in curve D of FIG. 3, the negativelyclamped waveform shown in curve C of FIG. 3 and the positively clampedwaveform as shown in cure E of FIG. 3 are identical to the respectivecurves D, C and E of FIG. 2 and remain the same independent of the inputsignals applied to the amplifier.

The positive signal V1 is supplied through the resistor R1 tothe base ofthe transistor Q1 at the point B. As can be seen in curve B of FIG. 3,the sum of the input signal V1-|- and the positive bias voltage B-latthe base of the transistor Q1 causes the waveform to be positive bymaximum amount (Vl-H-i-(B-H. Therefore, the waveform of curve B ispositive for a longer period of time as compared to the no input case.Therefore, the transistor Q1 is conductive for a longer period of time.Curve A of FIG. 3 shows the output pulse of the output transistor Q3produced in response to the conduction of the transistor Q1. It can beseen from curves A and B of FIG. 3 that both the leading and trailingedge of the Waveform of curve A of FIG. 3 are modulated, with leadingedge be ginning at a time sooner and the trailing edge lasting longer ascompared to the no input signal case shown in curve A of FIG. 2.

The input signal voltage of curve S1 of FIG. 3 being positive the su-mof the signals at the base of the transistor 32 at the point F is suchthat the base voltage never goes negative, and therefore, the transistorQ2 is not gated on. Since the transistor Q2 is not turned on the outputtransistor Q4 is also not turned on. Thus, no output pulse at the pointG at the collector of the transistor Q4, as shown in curve G of FIG. 3,is produced. With the input signal S1 remaining positive at the voltageV1+ until two input pulses are provided by the transistor Q3 as shown incurve A of FIG. 3, the output voltage as seen at the load impedance Zwill be as shown in curve H of FIG. 3` comprising two positive pulses ofthe same time duration as the pulses shown in curve A of FIG. 3.

As shown in curve S1 of FIG. 3 the input sginal goes to a negativepotential Vlat the time that the second pulse shown in curve A of FIG. 3is terminated. This causes the voltage at the point B at the base of thetransistor Q1 to be driven negatively thereby overcoming the biaspotential B+ and prohibiting the transistor Q1 from being gated on underthese conditions. Thus the output transistor Q3 is also not gated on nopositive output pulse is supplied from the transistor Q3 With thenegative input voltage V1- supplied to the amplifier. However referringto curve F of FIG. 3, the waveform thereof is driven negatively by thesummation of the negative input voltage Vland the negative bias voltageB- so that the transistor Q2 is driven into conduction during the timeperiod that the voltage at point F is negative. In response to theconduction of the transistor Q2, the output transistor Q4 is gated on toproduce a negative output pulse as shown in curve G of FIG. 3 of thetime duration dependent upon the time that the waveform of curve F ofFIG. 3 is negative.

Negative pulses will continue to be applied to the load impedance Z aslong as the negative input voltages V1- is applied to the amplifier. Itshould be noted that the pulse shown in curve G of FIG. 3 is double edgemodulated according to the time duration that the waveform F is negativeunder the influence of the negative input voltage V1-, the negative biasvoltage B- and the positive modulating signal shown in curve E of FIG.3. The composite output signals for the input signals as shown in curveS1 of FIG. 3 is shown in curve H of FIG. 3, and substantiallyreconstructs the input signals at an amplified output level.

In summary, the PWM a-mplifier described herein thus provides anamplified PWM output of the input signals applied thereto reconstructingthe input signals by double edge modulation.

Although the present invention has been described with a certain degreeof particularity, it should be understood that the present disclosurehas been made only by way of example and that numerous changes in thedetails of circuitry and the combination arrangement of parts, elementsand components can be resorted to without departing from the spirit andscope of the present invention.

I claim as my invention:

1. A pulse width modulated amplifier operative with input signalscomprising:

sawtooth means for providing modulating signals having a sawtoothwaveform alternating about a reference potential;

first means for providing first reference signals in response toclamping said modulating signals to said reference potential andpermitting excursions thereof in only one polarity; ysecond means forproviding second reference signals in response to clamping saidmodulating signals to said reference level and permitting excursionsthereof only in the opposite polarity from said first reference signals;third means for providing first and second biasing signals; firstchannel means for providing first control signals whose time duration isdependent upon the comparison of said input and said first biasingsignals with said first reference signals; second channel means forproviding second control signals whose time duration is dependent uponthe comparison of said input and said second biasing signals with saidsecond reference signals; and

output means for providing output signals to a load including first andsecond switching devices in response to the duration of said first andsecond control signals, respectively,

said first and second biasing signals being selected to provide arelatively small duty cycle of operation of said first and secondswitching devices in the absence of input signals being supplied to saidamplifier to effect thereby class A-B operation of said amplifier. 2.The amplifier of claim 1 wherein: said first biasing signals and saidfirst reference signals being of opposite polarities, and said secondbiasing signals and said second reference signals being of oppositepolarities.

3. The amplifier of claim 2 wherein:

said first means comprising a negative clamp circuit to clamp saidmodulating signals to said reference level and permit only negativeexcursions thereof,

said second means comprising a positive clamp circuit to clamp saidmodulating signals to said reference level and permit only positiveexcursions thereof.

4. The amplifier of claim 3 wherein:

said first biasing signals having a positive polarity and said secondbiasing signals having a negative polarity,

the duration of said first control signals being dependent upon the timethat the sum of said input signals and said first biasing signals ismore positive than the negative going said first reference signals,

the duration of said second control signals being dependent upon thetime that the sum of said input signals and said second biasing signalsis more negative than the positive going said second reference signals.

5. The amplifier of claim 4 wherein:

said switching devices including output and control electrodes,

`said load being operatively connected to an output electrode of each ofsaid devices to permit the bi- 10 lateral translation of currenttherethrough,

said first and second control signals being applied to the respectivecontrol electrodes of said devices to control the switching actionthereof.

References Cited UNITED STATES PATENTS ALFRED L. BRODY, Primary ExaminerU.S. Cl. X.R.

